The data integrity requirements for personal computer systems have grown rapidly in the past years. At the present time, newer operating systems and applications require a great deal of memory, and the amount of memory which can be accommodated in personal computer systems continues to increase rapidly. Such personal computer systems in the past have typically been provided only with the capability of writing and checking parity if even that. Added integrity requirements continue to increase the need for error correction code to be added to the system on the SIMM or DIMM cards so that errors occurring during the read cycle of data stored on the SIMM or DIMM are corrected before they are transmitted back to the CPU. One such system is shown in commonly assigned U.S. Pat. No. 5,450,422 which is incorporated herein by reference. In this system as in many others, error correction code is added to the SIMM and the correction of any errors, both hard errors and soft errors, takes place on the SIMM or DIMM card before the data is transmitted back to the CPU by the memory controller.
These ECC systems on SIMMs or DIMMs work quite well during operation. However one of the functions performed during power-on-self-tests (POST), is the detecting and flagging in some manner any errors in memory; and such errors will not normally be flagged or transmitted to the CPU if they are corrected by the ECC on the SIMM before the data is transmitted back to the CPU on a read cycle during POST. Thus the function of detecting errors in memory during POST is defeated when error correction takes place during the POST, since the system will not be notified of an error on the card during POST operations.
It is therefore a principle object of the present invention to provide a structure and method of flagging or trapping an error in the stored data in memory during a POST operation where the memory has on-board ECC and communicate that error and preferably the location thereof to the CPU during the POST cycle.